1. Field of Invention
The present invention relates to an Analog to Digital Converter (ADC) and particularly to a parallel ADC which will provide a means of achieving a high resolution at a relatively high speed.
2. Description of Prior Art
Prior analog to digital converters such as successive approximation or ramp can provide a high resolution. The techniques implemented by these ADC's provides a means of integrating them onto a single chip. This single chip solution enables designers to concentrate on more complex parts of their circuit. At that same time it provides a way of using less space on a PC board, improves the reliability of operation, and consumes less energy than a multi component ADC. The ramp ADC can provide a high resolution, however for each bit it uses it takes 2.sup.n (n=number of bits) clock pulses to convert each bit (i.e. 8 bits=256 clock pulses). This in effect means that a ramp ADC has a small bandwidth in respect to the resolution and therefore its uses are limited to analog signals which require low conversion rates such as a cruise control circuit in a car. The successive approximation ADC on the other hand provides a high resolution with the cost for each bit being one clock pulse per bit (i.e. 8 bits=8 clock pulses). This in effect means a successive approximation ADC has a larger bandwidth than a ramp ADC and can provide a much higher acquisition rate, which makes it a great ADC for conversions such as HiFi Audio Signals. Even though present technology successive approximation single chip ADC have a typical maximum conversions frequency of 500 KHz (time=2 .mu.s), this speed is not quite fast enough for conversions such as video. For the purpose of very high speed conversion such as video and other high frequency signals the Flash ADC (this includes Half Flash ADC) is the only existing type of ADC at the present time that can achieve these multi bit conversions at such speeds. The Flash ADC achieves its high performance through circuit complexity. That is it requires 2.sup.n -1 comparators and decoders to produce a Flash ADC of n bits (i.e. 16 bits requires 65,535 comparators and decoders). This poses a problem on present technology of how many comparators and decoders can fit into a small area on a chip, how the addition of each bit increases the power dissipation, how to deal with increase in temperature due to the power dissipation and the cost of production. For these reasons the Half Flash ADC was developed, it provides a solution to reducing the complexity of the circuitry used in a Flash ADC yet provides an acceptable acquisition rate for high speed conversions (the acquisition rate is approximately half the speed of the Flash ADC used in the Half Flash ADC). The Half Flash ADC achieves its performance at the cost of 2*(2.sup.n/2 -1) comparators and decoders to produce a Half Flash ADC of n bits (i.e. 16 bits requires 510 comparators decoders, a DAC of 8 bits, and other supporting circuitry). As seen from the previous examples, as the resolution is increased, the development of single chip Half Flash ADC is faced with the same type development flaws incurred in achieving higher resolutions in Flash ADC's. Therefore this leaves a gap to develop new techniques to achieve a higher resolution with conversions rates comparably close to that of Flash or Half Flash ADC's.